8 search results - page 1 / 2 » Towards Automated Power Gating of Registers using CoDeL |
ISCAS
2007
IEEE
14 years 5 months ago
2007
IEEE
— In this paper, we use the CoDeL platform to develop test circuits and analyze the potential and performance impact of power gating individual registers. For each register, we e...
SAMOS
2007
Springer
14 years 5 months ago
2007
Springer
In this paper, we use the CoDeL hardware design platform to analyze the potential and performance impact of power gating individual registers. For each register, we examine the per...
ISVLSI
2007
IEEE
14 years 5 months ago
2007
IEEE
— We present a performance analysis of CoDeL, a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. It automatically...
DAC
2000
ACM
15 years 3 days ago
2000
ACM
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
DAC
2009
ACM
15 years 4 days ago
2009
ACM
Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle ...