307 search results - page 59 / 62 » Towards Integrated Verification of Timed Transition Models |
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Simulation and verification using electronic design automation (EDA) tools are key steps in the design process for communication and signal processing systems. The synchronous dat...
TACAS
2010
Springer
13 years 5 months ago
2010
Springer
Abstract. We extend the setting of Satisfiability Modulo Theories (SMT) by introducing a theory of costs C, where it is possible to model and reason about resource consumption and ...
SIGGRAPH
1997
ACM
13 years 12 months ago
1997
ACM
This paper describes the integration of the Berkeley Architectural Walkthrough Program with the National Institute of Standards and Technology’s CFAST fire simulator. The integ...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people oft...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
The delay fault test pattern set generated by timing unaware commercial ATPG tools mostly affects very short paths, thereby increasing the escape chance of smaller delay defects. ...