133 search results - page 24 / 27 » Towards Nanoelectronics Processor Architectures |
APCSAC
2005
IEEE
14 years 1 months ago
2005
IEEE
Conditional branch induced control hazards cause significant performance loss in modern out-of-order superscalar processors. Dynamic branch prediction techniques help alleviate th...
SC
2000
ACM
13 years 12 months ago
2000
ACM
The current trend in HPC hardware is towards clusters of shared-memory (SMP) compute nodes. For applications developers the major question is how best to program these SMP cluster...
ISCA
2009
IEEE
14 years 2 months ago
2009
IEEE
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...
CC
2010
Springer
14 years 2 months ago
2010
Springer
On Chip Multiprocessors (CMP), it is common that multiple cores share certain levels of cache. The sharing increases the contention in cache and memory-to-chip bandwidth, further h...
IEEEPACT
2008
IEEE
14 years 1 months ago
2008
IEEE
Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that...