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ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
14 years 1 months ago
Multiple Instruction Stream Processor
Microprocessor design is undergoing a major paradigm shift towards multi-core designs, in anticipation that future performance gains will come from exploiting threadlevel parallel...
Richard A. Hankins, Gautham N. Chinya, Jamison D. ...
RAS
2008
108views more  RAS 2008»
13 years 7 months ago
Towards long-lived robot genes
Robot projects are often evolutionary dead ends, with the software and hardware they produce disappearing without trace afterwards. Common causes include dependencies on uncommon ...
Paul M. Fitzpatrick, Giorgio Metta, Lorenzo Natale
EUROPAR
2007
Springer
14 years 1 months ago
Toward Scalable Matrix Multiply on Multithreaded Architectures
We show empirically that some of the issues that affected the design of linear algebra libraries for distributed memory architectures will also likely affect such libraries for s...
Bryan Marker, Field G. Van Zee, Kazushige Goto, Gr...
CASES
2007
ACM
13 years 11 months ago
Towards understanding architectural tradeoffs in MEMS closed-loop feedback control
Micro-Electro-Mechanical Systems (MEMS) combine lithographically formed mechanical structures with electrical elements to create physical systems that operate on the scale of micr...
Greg Hoover, Forrest Brewer, Timothy Sherwood
CASES
2005
ACM
13 years 9 months ago
An Esterel processor with full preemption support and its worst case reaction time analysis
The concurrent synchronous language Esterel allows proto treat reactive systems in an abstract, concise manner. An Esterel program is typically first translated into other, non-s...
Xin Li, Jan Lukoschus, Marian Boldt, Michael Harde...