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DAC
2004
ACM
14 years 1 months ago
Extending the transaction level modeling approach for fast communication architecture exploration
System-on-Chip (SoC) designs are increasingly becoming more complex. Efficient on-chip communication architectures are critical for achieving desired performance in these systems....
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...
ANCS
2010
ACM
13 years 6 months ago
The case for hardware transactional memory in software packet processing
Software packet processing is becoming more important to enable differentiated and rapidly-evolving network services. With increasing numbers of programmable processor and acceler...
Martin Labrecque, J. Gregory Steffan
ICDCS
2007
IEEE
14 years 2 months ago
Resilient Cluster Formation for Sensor Networks
Sensor nodes are often organized into clusters to facilitate many network operations such as data aggregation. Clustering has to be protected in hostile environments. Otherwise, a...
Donggang Liu
TCS
1998
13 years 7 months ago
Conflict-Free Channel Set Assignment for an Optical Cluster Interconnection Network Based on Rotator Digraphs
Recently a class of scalable multi-star optical networks is proposed in [2]. In this class of networks nodes are grouped into clusters. Each cluster employs a separate pair of bro...
Peng-Jun Wan
SBACPAD
2008
IEEE
170views Hardware» more  SBACPAD 2008»
14 years 2 months ago
Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...
James Poe, Chang-Burm Cho, Tao Li