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» Transformational Placement and Synthesis
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ICCAD
1999
IEEE
80views Hardware» more  ICCAD 1999»
13 years 12 months ago
What is the cost of delay insensitivity?
Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behaviour. Asynchronous spee...
Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, ...
ICSM
1997
IEEE
13 years 12 months ago
Software Change Through Design Maintenance
Conventional software engineering tends to focus on a small part of the software life cycle: the design and implementation of a product. The bulk of the lifetime cost is in the ma...
Ira D. Baxter, Christopher Pidgeon
ASPDAC
2007
ACM
124views Hardware» more  ASPDAC 2007»
13 years 11 months ago
BddCut: Towards Scalable Symbolic Cut Enumeration
While the covering algorithm has been perfected recently by the iterative approaches, such as DAOmap and IMap, its application has been limited to technology mapping. The main fact...
Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown
CODES
2007
IEEE
13 years 11 months ago
Pointer re-coding for creating definitive MPSoC models
Today's MPSoC synthesis and exploration design flows start abstract input specification model captured in a system level design language. Usually this model is created from a...
Pramod Chandraiah, Rainer Dömer
FPL
2006
Springer
158views Hardware» more  FPL 2006»
13 years 11 months ago
Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed
FPGA devices exhibit manufacturing variability. Device ratings and Timing margins are typically used in order to cope with inter-device and intra-device variability respectively. ...
Evangelia Kassapaki, Pavlos M. Mattheakis, Christo...