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GD
1998
Springer
14 years 2 months ago
Using Graph Layout to Visualize Train Interconnection Data
We consider the problem of visualizing interconnections in railway systems. Given time tables from systems with thousands of trains, we are to visualize basic properties of the co...
Ulrik Brandes, Dorothea Wagner
ICCAD
1997
IEEE
144views Hardware» more  ICCAD 1997»
14 years 2 months ago
Exploiting off-chip memory access modes in high-level synthesis
Memory-intensive behaviors often contain large arrays that are synthesized into off-chip memories. With the increasing gap between on-chip and off-chip memory access delays, it is...
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nico...
MICRO
1997
IEEE
141views Hardware» more  MICRO 1997»
14 years 2 months ago
Unroll-and-Jam Using Uniformly Generated Sets
Modern architectural trends in instruction-level parallelism (ILP) are to increase the computational power of microprocessors significantly. As a result, the demands on memory ha...
Steve Carr, Yiping Guan
DAC
1997
ACM
14 years 2 months ago
Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...
Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha C...
STOC
1997
ACM
97views Algorithms» more  STOC 1997»
14 years 2 months ago
Using and Combining Predictors That Specialize
Abstract. We study online learning algorithms that predict by combining the predictions of several subordinate prediction algorithms, sometimes called “experts.” These simple a...
Yoav Freund, Robert E. Schapire, Yoram Singer, Man...