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DATE
2002
IEEE
98views Hardware» more  DATE 2002»
14 years 15 days ago
A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits
A unified approach to fault simulation for FGDs is introduced. Instead of a direct fault simulation, the proposed approach calculates indirectly from the simulator output the set...
Michael Pronath, Helmut E. Graeb, Kurt Antreich
DATE
2009
IEEE
163views Hardware» more  DATE 2009»
13 years 11 months ago
Analysis and optimization of fault-tolerant embedded systems with hardened processors
1 In this paper we propose an approach to the design optimization of fault-tolerant hard real-time embedded systems, which combines hardware and software fault tolerance techniques...
Viacheslav Izosimov, Ilia Polian, Paul Pop, Petru ...
PARELEC
2006
IEEE
14 years 1 months ago
A Fault-Tolerant Dynamic Fetch Policy for SMT Processors in Multi-Bus Environments
Modern microprocessors get more and more susceptible to transient faults, e.g. caused by high-energetic particles due to high integration, clock frequencies, temperature and decre...
Bernhard Fechner
EDCC
2008
Springer
13 years 9 months ago
Software Faults Diagnosis in Complex OTS Based Safety Critical Systems
This work addresses the problem of software fault diagnosis in complex safety critical software systems. The transient manifestations of software faults represent a challenging is...
Gabriella Carrozza, Domenico Cotroneo, Stefano Rus...
SRDS
1998
IEEE
13 years 11 months ago
System-Level Versus User-Defined Checkpointing
Checkpointing and rollback recovery is a very effective technique to tolerate transient faults and preventive shutdowns. In the past, most of the checkpointing schemes published i...
Luís Moura Silva, João Gabriel Silva