8 search results - page 1 / 2 » Translating between itanium and sparc memory consistency mod... |
SPAA
2006
ACM
14 years 10 months ago
2006
ACM
ASPLOS
2010
ACM
14 years 11 months ago
2010
ACM
Computer systems with virtual memory are susceptible to design bugs and runtime faults in their address translation (AT) systems. Detecting bugs and faults requires a clear speci�...
HPCA
1999
IEEE
14 years 9 months ago
1999
IEEE
Cache coherence protocols of current shared-memory multiprocessors are difficult to verify. Our previous work proposed an extension of Lamport's logical clocks for showing th...
CODES
2005
IEEE
14 years 10 months ago
2005
IEEE
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...
DAC
2003
ACM
15 years 5 months ago
2003
ACM
We present an algorithm that checks behavioral consistency between an ANSI-C program and a circuit given in Verilog using Bounded Model Checking. Both the circuit and the program ...