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» Translation validation for an optimizing compiler
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RSP
1999
IEEE
122views Control Systems» more  RSP 1999»
13 years 11 months ago
Incremental Compilation for Logic Emulation
Over the past decade, the steady growth rate of FPGA device capacities has enabled the development of multi-FPGA prototyping environments capable of implementing millions of logic...
Russell Tessier
TCAD
2008
127views more  TCAD 2008»
13 years 7 months ago
Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration
Abstract--Multimedia and DSP applications have several computationally intensive kernels which are often offloaded and accelerated by application-specific hardware. This paper pres...
Sejong Oh, Tag Gon Kim, Jeonghun Cho, Elaheh Bozor...
CASES
2007
ACM
13 years 11 months ago
Fragment cache management for dynamic binary translators in embedded systems with scratchpad
Dynamic binary translation (DBT) has been used to achieve numerous goals (e.g., better performance) for general-purpose computers. Recently, DBT has also attracted attention for e...
José Baiocchi, Bruce R. Childers, Jack W. D...
DAC
2009
ACM
14 years 4 days ago
Heterogeneous code cache: using scratchpad and main memory in dynamic binary translators
Dynamic binary translation (DBT) can be used to address important issues in embedded systems. DBT systems store translated code in a software-managed code cache. Unlike general-pu...
José Baiocchi, Bruce R. Childers
CGO
2011
IEEE
12 years 11 months ago
Extendable pattern-oriented optimization directives
Abstract—Current programming models and compiler technologies for multi-core processors do not exploit well the performance benefits obtainable by applying algorithm-specific, ...
Huimin Cui, Jingling Xue, Lei Wang, Yang Yang, Xia...