15 search results - page 2 / 3 » Transmission line design of clock trees |
GLVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
A sensitivity analysis of resonant H-tree clock distribution networks is presented in this paper for a TSMC 0.18 μm CMOS technology. The analysis focuses on the effect of the dri...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
— In this paper we consider the problem of finding a smaller RLCM circuit that approximately replicates the behavior (up to a certain frequency) of a given RLCM circuit. Targeted...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
—The clock distribution network is a key component of any synchronous VLSI design. High power dissipation and pressure volume temperature-induced variations in clock skew have st...
ISQED
2010
IEEE
13 years 5 months ago
2010
IEEE
This paper studies multi-core clock distribution using active deskewing methods. We propose an efficient methodology that uses Verilog-A to model PLLs, clock trees and power suppl...
ACSD
2005
IEEE
14 years 1 months ago
2005
IEEE
We present a bundled data communication scheme that is robust to crosstalk effects, and to manufacturing and environmental variations. Unlike a data bus, where each receiver alway...