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RTCSA
2007
IEEE
14 years 1 months ago
MB++: An Integrated Architecture for Pervasive Computing and High-Performance Computing
MB++ is a system that caters to the dynamic needs of applications in a distributed, pervasive computing environment that has a wide variety of devices that act as producers and co...
David J. Lillethun, David Hilley, Seth Horrigan, U...
IEEECIT
2010
IEEE
13 years 6 months ago
Developing a Cloud Computing Charging Model for High-Performance Computing Resources
Abstract—This paper examines the economics of cloud computing charging from the perspective of a supercomputing resource provider offering its own resources. To evaluate the comp...
Matthew Woitaszek, Henry M. Tufo
LCPC
2004
Springer
14 years 25 days ago
HiLO: High Level Optimization of FFTs
As computing platforms become more and more complex, the task of optimizing performance critical codes becomes more challenging. Recently, more attention has been focused on automa...
Nick Rizzolo, David A. Padua
FPL
2000
Springer
116views Hardware» more  FPL 2000»
13 years 11 months ago
High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs
Abstract. Field-programmable gate arrays (FPGAs) have become increasingly interesting in system design and due to the rapid technological progress ever larger devices are commercia...
Rolf Enzler, Tobias Jeger, Didier Cottet, Gerhard ...
ITC
2003
IEEE
116views Hardware» more  ITC 2003»
14 years 22 days ago
BIST for Deep Submicron ASIC Memories with High Performance Application
Today’s ASIC designs consist of more memory in terms of both area and number of instances. The shrinking of geometries has an even greater effect upon memories due to their tigh...
Theo J. Powell, Wu-Tung Cheng, Joseph Rayhawk, Ome...