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MICRO
2010
IEEE
156views Hardware» more  MICRO 2010»
13 years 6 months ago
Explicit Communication and Synchronization in SARC
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
Manolis Katevenis, Vassilis Papaefstathiou, Stamat...
NOMS
2008
IEEE
14 years 2 months ago
Optimizing request denial and latency in an agent-based VPN architecture
—Agent-based virtual private networks architecture (ABVA) refers to the environment where a third-party provider runs and administers remote access VPN service for organizations ...
Haiyang Qian, Steve Dispensa, Deep Medhi
ISCAS
2006
IEEE
118views Hardware» more  ISCAS 2006»
14 years 1 months ago
A robust continuous-time multi-dithering technique for laser communications using adaptive optics
A robust system architecture to achieve optical coherency free optimization. Several methods that had been proposed in the in multiple-beam free-space laser communication links wit...
Dimitrios N. Loizos, Paul-Peter Sotiriadis, Gert C...
CASES
2004
ACM
14 years 1 months ago
High-level power analysis for on-chip networks
As on-chip networks become prevalent in multiprocessor systemson-a-chip and multi-core processors, they will be an integral part of the design flow of such systems. With power in...
Noel Eisley, Li-Shiuan Peh
ISLPED
2003
ACM
115views Hardware» more  ISLPED 2003»
14 years 1 months ago
Reducing energy and delay using efficient victim caches
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
Gokhan Memik, Glenn Reinman, William H. Mangione-S...