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FPL
2004
Springer
205views Hardware» more  FPL 2004»
14 years 1 months ago
A System Level Resource Estimation Tool for FPGAs
Abstract. High level modeling tools make it possible to synthesize a high performance FPGA design directly from a Simulink model. Accurate estimates of the FPGA resources required ...
Changchun Shi, James Hwang, Scott McMillan, Ann Ro...
VTS
2002
IEEE
109views Hardware» more  VTS 2002»
14 years 23 days ago
Controlling Peak Power During Scan Testing
This paper presents a procedure for modifying a given set of scan vectors so that the peak power during scan testing is kept below a specified limit without reducing fault coverag...
Ranganathan Sankaralingam, Nur A. Touba
CONCUR
1999
Springer
14 years 4 days ago
Partial Order Reduction for Model Checking of Timed Automata
Abstract. The paper presents a partial order reduction method applicable to networks of timed automata. The advantage of the method is that it reduces both the number of explored c...
Marius Minea
DAC
2007
ACM
13 years 11 months ago
Skewed Flip-Flop Transformation for Minimizing Leakage in Sequential Circuits
Mixed Vt has been widely used to control leakage without affecting circuit performance. However, current approaches target the combinational circuits even though sequential elemen...
Jun Seomun, Jaehyun Kim, Youngsoo Shin
CAISE
2008
Springer
13 years 10 months ago
An Hybrid Design Solution For Spacecraft Simulators
Abstract. The European Space Agency (ESA) has created the Simulation Model Portability 2 (SMP2) standard with the purpose to provide a design solution for the project of Spacecraft...
Vitor Rodrigues, João Correia Lopes, Ana Mo...