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» Turning Back Time - What Impact on Performance
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111
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ISCA
2006
IEEE
138views Hardware» more  ISCA 2006»
15 years 9 months ago
Learning-Based SMT Processor Resource Distribution via Hill-Climbing
The key to high performance in Simultaneous Multithreaded (SMT) processors lies in optimizing the distribution of shared resources to active threads. Existing resource distributio...
Seungryul Choi, Donald Yeung
134
Voted
INFOCOM
2007
IEEE
15 years 10 months ago
Modeling Time-Variant User Mobility in Wireless Mobile Networks
Abstract— Realistic mobility models are important to understand the performance of routing protocols in wireless ad hoc networks, especially when mobility-assisted routing scheme...
Wei-jen Hsu, Thrasyvoulos Spyropoulos, Konstantino...
135
Voted
VTS
2002
IEEE
138views Hardware» more  VTS 2002»
15 years 8 months ago
Test Power Reduction through Minimization of Scan Chain Transitions
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test v...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...
118
Voted
WSC
2004
15 years 5 months ago
Assessing Obstacle Location Accuracy in the Remus Unmanned Underwater Vehicle
Navy personnel use the REMUS unmanned underwater vehicle to search for submerged objects. Navigation inaccuracies lead to errors in predicting the location of objects and thus inc...
Timothy E. Allen, Arnold H. Buss, Susan M. Sanchez
157
Voted
ASPLOS
2010
ACM
15 years 7 months ago
Micro-pages: increasing DRAM efficiency with locality-aware data placement
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
Kshitij Sudan, Niladrish Chatterjee, David Nellans...