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» Tutorial: Design of a Logic Synthesis System
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DATE
2005
IEEE
143views Hardware» more  DATE 2005»
14 years 29 days ago
Energy Bounds for Fault-Tolerant Nanoscale Designs
- The problem of determining lower bounds for the energy cost of a given nanoscale design is addressed via a complexity theory-based approach. This paper provides a theoretical fra...
Diana Marculescu
ITC
1999
IEEE
78views Hardware» more  ITC 1999»
13 years 11 months ago
Minimized power consumption for scan-based BIST
Power consumption of digital systems may increase significantly during testing. In this paper, systems equipped with a scan-based built-in self-test like the STUMPS architecture a...
Stefan Gerstendörfer, Hans-Joachim Wunderlich
TCAD
2008
118views more  TCAD 2008»
13 years 7 months ago
CHIPS: Custom Hardware Instruction Processor Synthesis
This paper describes an integer-linear-programming (ILP)-based system called Custom Hardware Instruction Processor Synthesis (CHIPS) that identifies custom instructions for critica...
Kubilay Atasu, Can C. Özturan, Günhan D&...
RSP
2005
IEEE
164views Control Systems» more  RSP 2005»
14 years 28 days ago
High Level Synthesis for Data-Driven Applications
Abstract— John von Neumann proposed his famous architecture in a context where hardware was very expensive and bulky. His goal was to maximize functionality with minimal hardware...
Etienne Bergeron, Xavier Saint-Mleux, Marc Feeley,...
POPL
2010
ACM
14 years 4 months ago
A Relational Modal Logic for Higher-Order Stateful ADTs
The method of logical relations is a classic technique for proving the equivalence of higher-order programs that implement the same observable behavior but employ different intern...
Derek Dreyer, Georg Neis, Andreas Rossberg, Lars B...