524 search results - page 24 / 105 » Two efficient methods to reduce power and testing time |
147
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ISQED
2005
IEEE
15 years 10 months ago
2005
IEEE
This paper proposes an efficient automation platform that provides fast and reliable path to analog circuit design for desired specifications. Circuit heuristics and hierarchy a...
118
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ISQED
2002
IEEE
15 years 9 months ago
2002
IEEE
This paper presents a hybrid BIST architecture and methods for optimizing it to test systems-on-chip in a cost effective way. The proposed self-test architecture can be implemente...
130
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ASPDAC
2007
ACM
15 years 8 months ago
2007
ACM
- Two methods to apply tests to detect delay faults in standard scan designs are used. One is called launch off capture and the other is called launch off shift. Launch off shift t...
144
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CF
2005
ACM
15 years 6 months ago
2005
ACM
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
152
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ITC
1996
IEEE
15 years 8 months ago
1996
IEEE
Abstract. In complex systems, embedded processors may be used to run software routines for test pattern generation and response evaluation. For system components which are not comp...