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» Two efficient methods to reduce power and testing time
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ECML
2006
Springer
15 years 8 months ago
Efficient Non-linear Control Through Neuroevolution
Abstract. Many complex control problems are not amenable to traditional controller design. Not only is it difficult to model real systems, but often it is unclear what kind of beha...
Faustino J. Gomez, Jürgen Schmidhuber, Risto ...
PAA
2006
15 years 4 months ago
Efficient median based clustering and classification techniques for protein sequences
Abstract In this paper, an efficient K-medians clustering (unsupervised) algorithm for prototype selection and Supervised K-medians (SKM) classification technique for protein seque...
P. A. Vijaya, M. Narasimha Murty, D. K. Subramania...
DAC
2005
ACM
16 years 5 months ago
Device and architecture co-optimization for FPGA power reduction
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
CHES
2000
Springer
121views Cryptology» more  CHES 2000»
15 years 8 months ago
On Boolean and Arithmetic Masking against Differential Power Analysis
Abstract. Since the announcement of the Differential Power Analysis (DPA) by Paul Kocher and al., several countermeasures were proposed in order to protect software implementations...
Jean-Sébastien Coron, Louis Goubin
ICCAD
1994
IEEE
121views Hardware» more  ICCAD 1994»
15 years 8 months ago
A cell-based power estimation in CMOS combinational circuits
In this paper we present a power dissipation model considering the charging/discharging of capacitance at the gate output node as well as internal nodes, and capacitance feedthrou...
Jiing-Yuan Lin, Tai-Chien Liu, Wen-Zen Shen