A programmable vector processor and its implementation with a field-programmable gate array (FPGA) are presented. This processor is composed of a vector core and a tightly couple...
Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the e...
Resonant clocking holds the promise of trading speed for energy in CMOS circuits that can afford to operate at low frequency, like hearing aids. An experimental chip with 110k tra...
Three-dimensional integrated circuits (3D ICs) provide an attractive solution for improving circuit performance. Such solutions must be embedded in an electrothermally-conscious d...
In this paper we introduce a tool which is capable of verifying an 1149.1 test logic implementation and its compliance to the IEEE 1149.1 Standard [1][2] while providing a precise...
Kevin Melocco, Hina Arora, Paul Setlak, Gary Kunse...