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ITNG
2007
IEEE
14 years 3 months ago
FPGA-based Vector Processing for Matrix Operations
A programmable vector processor and its implementation with a field-programmable gate array (FPGA) are presented. This processor is composed of a vector core and a tightly couple...
Hongyan Yang, Sotirios G. Ziavras, Jie Hu
FPGA
2007
ACM
153views FPGA» more  FPGA 2007»
14 years 3 months ago
Variation-aware routing for FPGAs
Chip design in the nanometer regime is becoming increasingly difficult due to process variations. ASIC designers have adopted statistical optimization techniques to mitigate the e...
Satish Sivaswamy, Kia Bazargan
DATE
2006
IEEE
95views Hardware» more  DATE 2006»
14 years 3 months ago
Two-phase resonant clocking for ultra-low-power hearing aid applications
Resonant clocking holds the promise of trading speed for energy in CMOS circuits that can afford to operate at low frequency, like hearing aids. An experimental chip with 110k tra...
Flavio Carbognani, Felix Bürgin, Norbert Felb...
ASPDAC
2006
ACM
166views Hardware» more  ASPDAC 2006»
14 years 3 months ago
Temperature-aware routing in 3D ICs
Three-dimensional integrated circuits (3D ICs) provide an attractive solution for improving circuit performance. Such solutions must be embedded in an electrothermally-conscious d...
Tianpei Zhang, Yong Zhan, Sachin S. Sapatnekar
ITC
2003
IEEE
123views Hardware» more  ITC 2003»
14 years 2 months ago
A Comprehensive Approach to Assessing and Analyzing 1149.1 Test Logic
In this paper we introduce a tool which is capable of verifying an 1149.1 test logic implementation and its compliance to the IEEE 1149.1 Standard [1][2] while providing a precise...
Kevin Melocco, Hina Arora, Paul Setlak, Gary Kunse...