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PARA
2004
Springer
14 years 2 months ago
Model Reduction for RF MEMS Simulation
Radio-frequency (RF) MEMS resonators, integrated into CMOS chips, are of great interest to engineers planning the next generation of communication systems. Fast simulations are nec...
David Bindel, Zhaojun Bai, James Demmel
PERCOM
2008
ACM
14 years 8 months ago
A tamper-proof and lightweight authentication scheme
We present a tamper-proof and lightweight challenge-response authentication scheme based on 2-level noisy Physically Unclonable Functions (PUF). We present a security reduction, w...
Ghaith Hammouri, Erdinç Öztürk, Berk Sunar
ISQED
2010
IEEE
194views Hardware» more  ISQED 2010»
14 years 3 months ago
Accelerating trace computation in post-silicon debug
— Post-silicon debug comprises a significant and highly variable fraction of the total development time for large chip designs. To accelerate post-silicon debug, BackSpace [1, 2...
Johnny J. W. Kuan, Steven J. E. Wilton, Tor M. Aam...
DSD
2006
IEEE
126views Hardware» more  DSD 2006»
14 years 2 months ago
Off-Line Testing of Delay Faults in NoC Interconnects
Testing of high density SoCs operating at high clock speeds is an important but difficult problem. Many faults, like delay faults, in such sub-micron chips may only appear when th...
Tomas Bengtsson, Artur Jutman, Shashi Kumar, Raimu...
WMPI
2004
ACM
14 years 2 months ago
A low cost, multithreaded processing-in-memory system
This paper discusses die cost vs. performance tradeoffs for a PIM system that could serve as the memory system of a host processor. For an increase of less than twice the cost of ...
Jay B. Brockman, Shyamkumar Thoziyoor, Shannon K. ...