Sciweavers

872 search results - page 44 / 175
» UML-based design test generation
Sort
View
ISPD
2000
ACM
92views Hardware» more  ISPD 2000»
15 years 8 months ago
An enhanced perturbing algorithm for floorplan design using the O-tree representation
Recently, a deterministic algorithm based on the O-tree representation has been proposed. This method generates excellent layout results on MCNC test cases with O(n3 ) complexity,...
Yingxin Pang, Chung-Kuan Cheng, Takeshi Yoshimura
ASPDAC
2006
ACM
141views Hardware» more  ASPDAC 2006»
15 years 8 months ago
Depth-driven verification of simultaneous interfaces
The verification of modern computing systems has grown to dominate the cost of system design, often with limited success as designs continue to be released with latent bugs. This t...
Ilya Wagner, Valeria Bertacco, Todd M. Austin
ITC
2002
IEEE
81views Hardware» more  ITC 2002»
15 years 9 months ago
Design Rewiring Using ATPG
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri
APAQS
2001
IEEE
15 years 8 months ago
End-to-End Integration Testing
Integration testing has always been a challenge especially if the system under test is large with many subsystems and interfaces. This paper proposes an approach to design End-toE...
Raymond A. Paul
ISSTA
2000
ACM
15 years 8 months ago
UML-Based integration testing
Increasing numbers of software developers are using the Unified Modeling Language (UML) and associated visual modeling tools as a basis for the design and implementation of their ...
Jean Hartmann, Claudio Imoberdorf, Michael Meising...