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» Ultra-low power digital subthreshold logic circuits
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DATE
2005
IEEE
116views Hardware» more  DATE 2005»
14 years 2 months ago
Uniformly-Switching Logic for Cryptographic Hardware
Recent work on Differential Power Analysis shows that even mathematically-secure cryptographic protocols may be vulnerable at the physical implementation level. By measuring energ...
Igor L. Markov, Dmitri Maslov
ISCAS
2005
IEEE
185views Hardware» more  ISCAS 2005»
14 years 2 months ago
2 GHz 8-bit CMOS ROM-less direct digital frequency synthesizer
—This paper presents a 2GHz 8-bit CMOS ROM-less direct digital frequency synthesizer (DDFS). Nonlinear current steering digital to analog converter (DAC) has been utilized to con...
Xuefeng Yu, Foster F. Dai, Yin Shi, Ronghua Zhu
CDES
2006
240views Hardware» more  CDES 2006»
13 years 10 months ago
Design of Low Power 4-Tap 8-Bit Adiabatic FIR Filter
Abstract-- Digital signal processing (DSP) is used to perform filtering, decimation and down conversion in common communications systems, like in oversampling analog to digital con...
Arun N. Chandorkar, Gurvinder Singh
DAC
1997
ACM
14 years 1 months ago
Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...
Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha C...
FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
14 years 5 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson