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WWW
2007
ACM
16 years 3 months ago
Improving the Performance of Online Auctions Through Server-side Activity-based Caching
Online auction sites have very specific workloads and user behavior characteristics. Previous studies on workload characterization conducted by the authors showed that i) bidding a...
Daniel A. Menascé, Vasudeva Akula
ISCA
1998
IEEE
145views Hardware» more  ISCA 1998»
15 years 6 months ago
Multi-Level Texture Caching for 3D Graphics Hardware
Traditional graphics hardware architectures implement what we call the push architecture for texture mapping. Local memory is dedicated to the accelerator for fast local retrieval...
Michael Cox, Narendra Bhandri, Michael Shantz
SIGOPS
2010
179views more  SIGOPS 2010»
14 years 9 months ago
Online cache modeling for commodity multicore processors
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
Richard West, Puneet Zaroo, Carl A. Waldspurger, X...
174
Voted
TVLSI
2010
14 years 9 months ago
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris...
SLP
1997
78views more  SLP 1997»
15 years 3 months ago
Using SimICS to Evaluate the Penny System
We demonstrate the bene ts of instruction-set simulation in the evaluation of a parallel programming system, Penny. The simulator is a reliable tool in exploring design alternativ...
Johan Montelius, Peter S. Magnusson