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VLSID
2001
IEEE
118views VLSI» more  VLSID 2001»
14 years 10 months ago
Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language
Memory represents a major bottleneck in modern embedded systems. Traditionally, memory organizationsfor programmable systems assumed a fixed cache hierarchy. Withthe wideningproce...
Prabhat Mishra, Peter Grun, Nikil D. Dutt, Alexand...
HPCA
2007
IEEE
14 years 10 months ago
A Scalable, Non-blocking Approach to Transactional Memory
Transactional Memory (TM) provides mechanisms that promise to simplify parallel programming by eliminating the need for locks and their associated problems (deadlock, livelock, pr...
Hassan Chafi, Jared Casper, Brian D. Carlstrom, Au...
OSDI
2004
ACM
14 years 10 months ago
Middleboxes No Longer Considered Harmful
Intermediate network elements, such as network address translators (NATs), firewalls, and transparent caches are now commonplace. The usual reaction in the network architecture co...
Michael Walfish, Jeremy Stribling, Maxwell N. Kroh...
VLDB
2003
ACM
123views Database» more  VLDB 2003»
14 years 10 months ago
A case for fractured mirrors
The Decomposition Storage Model (DSM) vertically partitions all attributes of a given relation. DSM has excellent I/O behavior when the number of attributes touched in the query i...
Ravishankar Ramamurthy, David J. DeWitt, Qi Su
ICCD
2005
IEEE
108views Hardware» more  ICCD 2005»
14 years 7 months ago
Methods for Modeling Resource Contention on Simultaneous Multithreading Processors
Simultaneous multithreading (SMT) seeks to improve the computation throughput of a processor core by sharing primary resources such as functional units, issue bandwidth, and cache...
Tipp Moseley, Dirk Grunwald, Joshua L. Kihm, Danie...