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DATE
2000
IEEE
142views Hardware» more  DATE 2000»
14 years 1 months ago
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
Balakrishna Kumthekar, Fabio Somenzi
RTCSA
2000
IEEE
14 years 1 months ago
Optimal scheduling of imprecise computation tasks in the presence of multiple faults
With the advance of applications such as multimedia, imagelspeech processing and real-time AI, real-time computing models allowing to express the “timeliness versus precision”...
Hakan Aydin, Rami G. Melhem, Daniel Mossé
PLDI
2000
ACM
14 years 1 months ago
Safety checking of machine code
We show how to determine statically whether it is safe for untrusted machine code to be loaded into a trusted host system. Our safety-checking technique operates directly on the u...
Zhichen Xu, Barton P. Miller, Thomas W. Reps
AGP
1999
IEEE
14 years 1 months ago
Widening Sharing
We study the problem of an efficient and precise sharing analysis of (constraint) logic programs. After recognizing that neither aring nor its non-redundant (but equivalent) abstra...
Enea Zaffanella, Roberto Bagnara, Patricia M. Hill
FCCM
1999
IEEE
111views VLSI» more  FCCM 1999»
14 years 1 months ago
Optimizing FPGA-Based Vector Product Designs
This paper presents a method, called multiple constant multiplier trees MCMTs, for producing optimized recon gurable hardware implementations of vector products. An algorithm for ...
Dan Benyamin, John D. Villasenor, Wayne Luk