Sciweavers

1052 search results - page 20 / 211
» Understanding POWER multiprocessors
Sort
View
DATE
2009
IEEE
138views Hardware» more  DATE 2009»
14 years 2 months ago
Hardware/software co-design architecture for thermal management of chip multiprocessors
—The sustained push for performance, transistor count, and instruction level parallelism has reached a point where chip level power density issues are at the forefront of design ...
Omer Khan, Sandip Kundu
DATE
2008
IEEE
99views Hardware» more  DATE 2008»
14 years 2 months ago
Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures
As feature sizes decrease, power dissipation and heat generation density exponentially increase. Thus, temperature gradients in Multiprocessor Systems on Chip (MPSoCs) can serious...
Fabrizio Mulas, Michele Pittau, Marco Buttu, Salva...
ASPDAC
2009
ACM
117views Hardware» more  ASPDAC 2009»
14 years 9 days ago
Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications
– The phenomenon of digital convergence and increasing application complexity today is motivating the design of chip multiprocessor (CMP) applications with multiple use cases. Mo...
Sudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi
ECRTS
2010
IEEE
13 years 8 months ago
Partitioning Parallel Applications on Multiprocessor Reservations
A full exploitation of the computational power available in a multi-core platform requires the software to be specified in terms of parallel execution flows. At the same time, mode...
Giorgio C. Buttazzo, Enrico Bini, Yifan Wu
PDP
2011
IEEE
12 years 11 months ago
Energy-Aware Task Allocation for Network-on-Chip Based Heterogeneous Multiprocessor Systems
—Energy-efficiency is becoming one of the most critical issues in embedded system design. In Network-on-Chip (NoC) based heterogeneous Multiprocessor Systems, the energy consump...
Jia Huang, Christian Buckl, Andreas Raabe, Alois K...