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DSD
2008
IEEE
124views Hardware» more  DSD 2008»
14 years 2 months ago
A Modular Approach to Model Heterogeneous MPSoC at Cycle Level
This paper proposes a system-level cycle-based framework to model and design heterogeneous Multiprocessor Systems on-Chip (MPSoC), called GRAPES. The approach features flexibilit...
Matteo Monchiero, Gianluca Palermo, Cristina Silva...
CODES
2007
IEEE
14 years 2 months ago
Performance analysis and design space exploration for high-end biomedical applications: challenges and solutions
High-end biomedical applications are a good target for specificpurpose system-on-chip (SoC) implementations. Human heart electrocardiogram (ECG) real-time monitoring and analysis ...
Iyad Al Khatib, Davide Bertozzi, Axel Jantsch, Luc...
IPPS
2007
IEEE
14 years 2 months ago
RAxML-Cell: Parallel Phylogenetic Tree Inference on the Cell Broadband Engine
Computational phylogeny is a challenging application even for the most powerful supercomputers. It is also an ideal candidate for benchmarking emerging multiprocessor architecture...
Filip Blagojevic, Alexandros Stamatakis, Christos ...
HICSS
2006
IEEE
164views Biometrics» more  HICSS 2006»
14 years 1 months ago
A Methodology for Generating Application-Specific Heterogeneous Processor Arrays
Hardware designers are increasingly turning to Single Chip Multi-Processors to achieve power and throughput goals. To further increase performance for a specific application the c...
Stephen D. Craven, Cameron Patterson, Peter M. Ath...
TVCG
2010
151views more  TVCG 2010»
13 years 2 months ago
Interactive Visual Analysis of Multiple Simulation Runs Using the Simulation Model View: Understanding and Tuning of an Electron
Multiple simulation runs using the same simulation model with different values of control parameters usually generate large data sets that capture the variational aspects of the be...
Kresimir Matkovic, Denis Gracanin, Mario Jelovic, ...