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ASPDAC
2009
ACM
115views Hardware» more  ASPDAC 2009»
13 years 8 months ago
Frequent value compression in packet-based NoC architectures
The proliferation of Chip Multiprocessors (CMPs) has led to the integration of large on-chip caches. For scalability reasons, a large on-chip cache is often divided into smaller ba...
Ping Zhou, Bo Zhao, Yu Du, Yi Xu, Youtao Zhang, Ju...
ACIVS
2006
Springer
14 years 1 months ago
Context-Based Scene Recognition Using Bayesian Networks with Scale-Invariant Feature Transform
Scene understanding is an important problem in intelligent robotics. Since visual information is uncertain due to several reasons, we need a novel method that has robustness to the...
Seung-Bin Im, Sung-Bae Cho
FDL
2005
IEEE
14 years 3 months ago
Automatic synthesis of the Hardware/Software Interface
Although Moore’s Law enables a huge number of components to be integrated into a single chip, design methods that will allow system architects to put the components together to ...
Francesco Regazzoni, André C. Nácul,...
IEEEPACT
2002
IEEE
14 years 3 months ago
Efficient Interconnects for Clustered Microarchitectures
Clustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we inv...
Joan-Manuel Parcerisa, Julio Sahuquillo, Antonio G...
VR
1999
IEEE
119views Virtual Reality» more  VR 1999»
14 years 2 months ago
Virtual Flythrough over a Voxel-Based Terrain
A voxel-based terrain visualization system is presented with real-time performance on general-purpose graphics multiprocessor workstations. Ray casting of antialiased 3D volume te...
Ming Wan, Huamin Qu, Arie E. Kaufman