65 search results - page 6 / 13 » Unified decoder architecture for LDPC turbo codes |
ISLPED
2003
ACM
14 years 27 days ago
2003
ACM
Presented in this paper is a low-power architecture for turbo decodings of parallel concatenated convolutional codes. The proposed architecture is derived via the concept of block...
ISCAS
2011
IEEE
12 years 11 months ago
2011
IEEE
—We propose a multi-layer parallel decoding algorithm and VLSI architecture for decoding of structured quasi-cyclic low-density parity-check codes. In the conventional layered de...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
— The fully parallel LDPC decoding architecture can achieve high decoding throughput, but it suffers from large hardware complexity caused by a large set of processing units and ...
VLSID
2005
IEEE
14 years 8 months ago
2005
IEEE
Low-Density Parity Check codes are a form of Error Correcting Codes used in various wireless communication applications and in disk drives. While LDPC codes are desirable due to t...
MCSS
2009
Springer
14 years 6 days ago
2009
Springer
Abstract Braided convolutional codes (BCCs) form a class of iteratively decodable convolutional codes that are constructed from component convolutional codes. In braided code divis...