65 search results - page 9 / 13 » Unified decoder architecture for LDPC turbo codes |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents a new multiprocessor platform for high throughput turbo decoding. The proposed platform is based on a new configurable ASIP combined with an efficient memory a...
FCCM
2004
IEEE
13 years 11 months ago
2004
IEEE
We describe a flexible hardware encoder for regular and irregular low-density parity-check (LDPC) codes. Although LDPC codes achieve achieve better performance and lower decoding ...
ASAP
2006
IEEE
13 years 9 months ago
2006
IEEE
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
The design of future communication systems with high throughput demands will become a critical task, especially when sophisticated channel coding schemes have to be applied. LDPC ...
ICC
2008
IEEE
14 years 2 months ago
2008
IEEE
Abstract— The design of LDPC decoders with low complexity, high throughput, and good performance is a critical task. A well-known strategy is to design structured codes such as q...