720 search results - page 110 / 144 » Uniform Memory Hierarchies |
131
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MICRO
2009
IEEE
15 years 11 months ago
2009
IEEE
Aggressive prefetching is very beneficial for memory latency tolerance of many applications. However, it faces significant challenges in multi-core systems. Prefetchers of diff...
142
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EUROPAR
2009
Springer
15 years 11 months ago
2009
Springer
An upgrade from dual-core to quad-core AMD processor on the Cray XT system at the Oak Ridge National Laboratory (ORNL) Leadership Computing Facility (LCF) has resulted in significa...
159
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DATE
2008
IEEE
15 years 11 months ago
2008
IEEE
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
128
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ICPP
2008
IEEE
15 years 10 months ago
2008
IEEE
The slow speed of conventional execution-driven architecture simulators is a serious impediment to obtaining desirable research productivity. This paper proposes and evaluates a f...
142
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CGO
2007
IEEE
15 years 10 months ago
2007
IEEE
Emerging microprocessors offer unprecedented parallel computing capabilities and deeper memory hierarchies, increasing the importance of loop transformations in optimizing compile...