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ISPD
2006
ACM
175views Hardware» more  ISPD 2006»
14 years 2 months ago
mPL6: enhanced multilevel mixed-size placement
The multilevel placement package mPL6 combines improved implementations of the global placer mPL5 (ISPD05) and the XDP legalizer and detailed placer (ASPDAC06). It consistently pr...
Tony F. Chan, Jason Cong, Joseph R. Shinnerl, Kent...
ICCAD
2003
IEEE
109views Hardware» more  ICCAD 2003»
14 years 5 months ago
Large-Scale Circuit Placement: Gap and Promise
Placement is one of the most important steps in the RTLto-GDSII synthesis process, as it directly defines the interconnects, which have become the bottleneck in circuit and syste...
Jason Cong, Tim Kong, Joseph R. Shinnerl, Min Xie,...
SACMAT
2009
ACM
14 years 3 months ago
Supporting RBAC with XACML+OWL
XACML does not natively support RBAC and even the specialized XACML profiles are not able to support many relevant constraints such as static and dynamic separation of duty. Exte...
Rodolfo Ferrini, Elisa Bertino
ECBS
2007
IEEE
161views Hardware» more  ECBS 2007»
13 years 10 months ago
Alert Fusion for a Computer Host Based Intrusion Detection System
Intrusions impose tremendous threats to today’s computer hosts. Intrusions using security breaches to achieve unauthorized access or misuse of critical information can have cata...
Chuan Feng, Jianfeng Peng, Haiyan Qiao, Jerzy W. R...
TCAD
2008
93views more  TCAD 2008»
13 years 8 months ago
Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion
Starting at the 65-nm node, stress engineering to improve the performance of transistors has been a major industry focus. An intrinsic stress source--shallow trench isolation (STI)...
Andrew B. Kahng, Puneet Sharma, Rasit Onur Topalog...