112 search results - page 2 / 23 » Use of local biasing in designing analog integrated circuits |
DATE
2010
IEEE
13 years 12 months ago
2010
IEEE
Abstract—This article discusses system-level techniques to optimize the power-performance trade-off in subthreshold circuits and presents a uniform platform for implementing ultr...
ISCAS
2005
IEEE
14 years 14 days ago
2005
IEEE
We propose an analog current-mode subthreshold CMOS circuit implementing a neuromorphic oscillator. Our circuit is based on the half-center oscillator model proposed by Matsuoka, ...
ISCAS
2003
IEEE
14 years 5 days ago
2003
IEEE
The designer needs simple and accurate models to estimate noise in MOS transistors as a function of their size, bias point and technology. In this work, we present a simple, conti...
DAC
1999
ACM
13 years 11 months ago
1999
ACM
This paper presents a method to reduce the complexity of a linear or linearized (small-signal) analog circuit. The reduction technique, based on quality-error ranking, can be used...
ISQED
2000
IEEE
2000
IEEE
A Layout Approach for Electrical and Physical Design Integration of High-Performance Analog Circuits
13 years 11 months ago
This paper presents a layout generation tool that aims to reduce the gap between electrical sizing and physical realization of high performance analog circuits. The procedural lay...