490 search results - page 30 / 98 » User-Driven Frequency Scaling |
122
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DAC
2004
ACM
15 years 9 months ago
2004
ACM
The Pentium® 4 processor architecture uses a 2x frequency core clock[1] to implement low latency integer ops. Low Voltage Swing logic circuits implemented in 90nm technology[2] m...
145
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EUC
2008
Springer
15 years 5 months ago
2008
Springer
A generalized dynamic energy performance scaling (DEPS) framework is proposed for exploring applicationspecific energy-saving potential in hard real-time embedded systems. This so...
155
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TII
2010
14 years 10 months ago
2010
Abstract--CPU utilization control has recently been demonstrated to be an effective way of meeting end-to-end deadlines for distributed real-time systems running in unpredictable e...
121
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ICCD
2007
IEEE
15 years 7 months ago
2007
IEEE
This paper presents a novel power reduction method for chip multi-processors (CMPs) under real-time constraints. While the power consumption of processing units (PUs) on CMPs can ...
110
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DAC
2004
ACM
16 years 4 months ago
2004
ACM
We investigate trade-offs in microprocessor frequency and system power achievable for low temperature operation in scaled high leakage technologies by combining refrigeration with...