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GLVLSI
2009
IEEE
125views VLSI» more  GLVLSI 2009»
14 years 2 months ago
Timing-driven N-way decomposition
Logic decomposition has been extensively used to optimize the worst-case delay and the area in the technology independent phase. Bi-decomposition is one of the state-of-art techni...
David Bañeres, Jordi Cortadella, Michael Ki...
DAC
2007
ACM
14 years 8 months ago
Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis
It is known that ramp-based models are not sufficient for accurate timing modeling. In this paper, we develop a technique that accurately models the waveforms, and also allows a f...
Anand Ramalingam, Ashish Kumar Singh, Sani R. Nass...
VLSID
2009
IEEE
155views VLSI» more  VLSID 2009»
14 years 8 months ago
Unified Challenges in Nano-CMOS High-Level Synthesis
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
Saraju P. Mohanty
CODES
2006
IEEE
14 years 1 months ago
Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations
Process variability has a detrimental impact on the performance of memories and other system components, which can lead to parametric yield loss at the system level due to timing ...
Antonis Papanikolaou, T. Grabner, Miguel Miranda, ...
GLVLSI
2009
IEEE
103views VLSI» more  GLVLSI 2009»
14 years 2 months ago
Enhancing bug hunting using high-level symbolic simulation
The miniaturization of transistors in recent technology nodes requires tremendous back-end tuning and optimizations, making bug fixing at later design stages more expensive. Ther...
Hong-Zu Chou, I-Hui Lin, Ching-Sung Yang, Kai-Hui ...