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» Using Eigenvectors to Partition Circuits
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DATE
2010
IEEE
110views Hardware» more  DATE 2010»
14 years 1 months ago
Enabling efficient post-silicon debug by clustering of hardware-assertions
—Bug-free first silicon is not guaranteed by the existing pre-silicon verification techniques. To have impeccable products, it is now required to identify any bug as soon as the ...
Mohammad Hossein Neishaburi, Zeljko Zilic
ASPDAC
2004
ACM
113views Hardware» more  ASPDAC 2004»
14 years 10 days ago
Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction
- Minimum area is one of the important objectives in technology mapping for lookup table-based FPGAs. It has been proven that the problem is NP-complete. This paper presents a poly...
Chi-Chou Kao, Yen-Tai Lai
INTEGRATION
2007
90views more  INTEGRATION 2007»
13 years 8 months ago
Partitioning-based decoupling capacitor budgeting via sequence of linear programming
In this paper, we propose an efficient algorithm to reduce the voltage noises for on-chip power/ground (P/G) networks of VLSI. The new method is based on the sequence of linear p...
Jeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong...
ICCAD
1994
IEEE
95views Hardware» more  ICCAD 1994»
14 years 21 days ago
Provably correct high-level timing analysis without path sensitization
- This paper addresses the problem of true delay estimation during high level design. The existing delay estimation techniques either estimate the topological delay of the circuit ...
Subhrajit Bhattacharya, Sujit Dey, Franc Brglez
FCCM
2005
IEEE
139views VLSI» more  FCCM 2005»
14 years 2 months ago
A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation
Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan