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HEURISTICS
2008
136views more  HEURISTICS 2008»
13 years 7 months ago
Enhancing set constraint solvers with lexicographic bounds
Since their beginning in constraint programming, set solvers have been applied to a wide range of combinatorial search problems, such as bin-packing, set partitioning, circuit desi...
Andrew Sadler, Carmen Gervet
DAC
2009
ACM
14 years 9 months ago
Event-driven gate-level simulation with GP-GPUs
Logic simulation is a critical component of the design tool flow in modern hardware development efforts. It is used widely ? from high-level descriptions down to gate-level ones ?...
Debapriya Chatterjee, Andrew DeOrio, Valeria Berta...
ICCAD
2004
IEEE
180views Hardware» more  ICCAD 2004»
14 years 5 months ago
Physical placement driven by sequential timing analysis
Traditional timing-driven placement considers only combinational delays and does not take into account the potential of subsequent sequential optimization steps. As a result, the ...
Aaron P. Hurst, Philip Chong, Andreas Kuehlmann
ASAP
2008
IEEE
142views Hardware» more  ASAP 2008»
14 years 3 months ago
Managing multi-core soft-error reliability through utility-driven cross domain optimization
As semiconductor processing technology continues to scale down, managing reliability becomes an increasingly difficult challenge in high-performance microprocessor design. Transie...
Wangyuan Zhang, Tao Li
PADS
2003
ACM
14 years 1 months ago
DVS: An Object-Oriented Framework for Distributed Verilog Simulation
There is a wide-spread usage of hardware design languages(HDL) to speed up the time-to-market for the design of modern digital systems. Verification engineers can simulate hardwa...
Lijun Li, Hai Huang, Carl Tropper