643 search results - page 111 / 129 » Using Hardware Counters to Automatically Improve Memory Perf... |
DAMON
2007
Springer
14 years 3 months ago
2007
Springer
Recently, graphics processing units, or GPUs, have become a viable alternative as commodity, parallel hardware for generalpurpose computing, due to their massive data-parallelism,...
DSD
2002
IEEE
14 years 1 months ago
2002
IEEE
Modern microprocessors schedule instructions dynamically in order to exploit instruction-level parallelism. It is necessary to increase instruction window size for improving instr...
ISCA
2002
IEEE
14 years 1 months ago
2002
IEEE
An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory (CAM) arrays accessed during instruction wakeup. The performance of th...
FPL
2007
Springer
14 years 22 days ago
2007
Springer
Recently, there is a surge of interests in using FPGAs for computer architecture research including applications from emulating and analyzing a new platform to accelerating microa...
IEEEPACT
2006
IEEE
14 years 2 months ago
2006
IEEE
Static Single Assignment (SSA) has become the intermediate program representation of choice in most modern compilers because it enables efficient data flow analysis of scalars an...