643 search results - page 18 / 129 » Using Hardware Counters to Automatically Improve Memory Perf... |
ISCA
1989
IEEE
14 years 19 days ago
1989
IEEE
Most current single-chip processors employ an on-chip instruction cache to improve performance. A miss in this insk-uction cache will cause an external memory reference which must...
CODES
2007
IEEE
14 years 2 months ago
2007
IEEE
With growing capacities of flash memories, an efficient layer to manage read and write access to flash is required. NFTL is a widely used block based flash translation layer de...
ICDE
2006
IEEE
14 years 10 months ago
2006
IEEE
The rapid increase in the data volumes for the past few decades has intensified the need for high processing power for database and data mining applications. Researchers have acti...
DAC
2002
ACM
14 years 9 months ago
2002
ACM
An architectural solution to reducing memory energy consumption is to adopt a multi-bank memory system instead of a monolithic (single-bank) memory system. Some recent multi-bank ...
ISCA
2009
IEEE
14 years 3 months ago
2009
IEEE
The widespread use of multicore processors has dramatically increased the demands on high bandwidth and large capacity from memory systems. In a conventional DDR2/DDR3 DRAM memory...