Sciweavers

643 search results - page 20 / 129
» Using Hardware Counters to Automatically Improve Memory Perf...
Sort
View
PDP
2005
IEEE
14 years 2 months ago
Memory Bandwidth Aware Scheduling for SMP Cluster Nodes
Clusters of SMPs are becoming increasingly common. However, the shared memory design of SMPs and the consequential contention between system processors for access to main memory c...
Evangelos Koukis, Nectarios Koziris
ASPDAC
2011
ACM
217views Hardware» more  ASPDAC 2011»
13 years 6 days ago
Realization and performance comparison of sequential and weak memory consistency models in network-on-chip based multi-core syst
This paper studies realization and performance comparison of the sequential and weak consistency models in the network-on-chip (NoC) based distributed shared memory (DSM) multi-cor...
Abdul Naeem, Xiaowen Chen, Zhonghai Lu, Axel Jants...
CASES
2003
ACM
14 years 1 months ago
Frequent loop detection using efficient non-intrusive on-chip hardware
Dynamic software optimization methods are becoming increasingly popular for improving software performance and power. The first step in dynamic optimization consists of detecting ...
Ann Gordon-Ross, Frank Vahid
ACSD
2007
IEEE
109views Hardware» more  ACSD 2007»
14 years 19 days ago
Efficient Automatic Resolution of Encoding Conflicts Using STG Unfoldings
Synthesis of asynchronous circuits from Signal Transition Graphs (STGs) involves resolution of state encoding conflicts by means of refining the STG specification. In this paper, ...
Victor Khomenko
ISCA
2002
IEEE
115views Hardware» more  ISCA 2002»
14 years 1 months ago
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery
We develop an availability solution, called SafetyNet, that uses a unified, lightweight checkpoint/recovery mechanism to support multiple long-latency fault detection schemes. At...
Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, ...