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WSCG
2004
161views more  WSCG 2004»
13 years 10 months ago
Rendering Techniques for Hardware-Accelerated Image-Based CSG
Image-based CSG rendering algorithms for standard graphics hardware rely on multipass rendering that includes reading and writing large amounts of pixel data from and to the frame...
Florian Kirsch, Jürgen Döllner
DATE
2008
IEEE
114views Hardware» more  DATE 2008»
14 years 3 months ago
Operating System Controlled Processor-Memory Bus Encryption
—Unencrypted data appearing on the processor– memory bus can result in security violations, e.g., allowing attackers to gather keys to financial accounts and personal data. Al...
Xi Chen, Robert P. Dick, Alok N. Choudhary
DATE
2006
IEEE
202views Hardware» more  DATE 2006»
14 years 2 months ago
Automatic systemC design configuration for a faster evaluation of different partitioning alternatives
In this paper we present a methodology that is based on SystemC [1] for rapid prototyping to greatly enhance and accelerate the exploration of complex systems to optimize the syst...
Nico Bannow, Karsten Haug, Wolfgang Rosenstiel
ASPDAC
2008
ACM
108views Hardware» more  ASPDAC 2008»
13 years 10 months ago
Synthesis and design of parameter extractors for low-power pre-computation-based content-addressable memory using gate-block sel
Content addressable memory (CAM) is frequently used in applications, such as lookup tables, databases, associative computing, and networking, that require high-speed searches due t...
Jui-Yuan Hsieh, Shanq-Jang Ruan
DATE
2003
IEEE
117views Hardware» more  DATE 2003»
14 years 1 months ago
Exploring SW Performance Using SoC Transaction-Level Modeling
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
Imed Moussa, Thierry Grellier, Giang Nguyen