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DATE
2004
IEEE
159views Hardware» more  DATE 2004»
14 years 12 days ago
Compositional Memory Systems for Data Intensive Applications
To alleviate the system performance unpredictability of multitasking applications running on multiprocessor platforms with shared memory hierarchies we propose a task level set ba...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...
IEEEPACT
2002
IEEE
14 years 1 months ago
Using the Compiler to Improve Cache Replacement Decisions
Memory performance is increasingly determining microprocessor performance and technology trends are exacerbating this problem. Most architectures use set-associative caches with L...
Zhenlin Wang, Kathryn S. McKinley, Arnold L. Rosen...
MICRO
2007
IEEE
188views Hardware» more  MICRO 2007»
14 years 2 months ago
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding
In deep sub-micron ICs, growing amounts of ondie memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. As scaling progresses...
Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Fal...
ISCA
2007
IEEE
174views Hardware» more  ISCA 2007»
14 years 3 months ago
An integrated hardware-software approach to flexible transactional memory
There has been considerable recent interest in the support of transactional memory (TM) in both hardware and software. We present an intermediate approach, in which hardware is us...
Arrvindh Shriraman, Michael F. Spear, Hemayet Hoss...
PADL
2004
Springer
14 years 2 months ago
Improved Compilation of Prolog to C Using Moded Types and Determinism Information
We describe the current status of and provide performance results for a prototype compiler of Prolog to C, ciaocc. ciaocc is novel in that it is designed to accept different kinds...
José F. Morales, Manuel Carro, Manuel V. He...