Sciweavers

643 search results - page 58 / 129
» Using Hardware Counters to Automatically Improve Memory Perf...
Sort
View
ITC
1992
IEEE
76views Hardware» more  ITC 1992»
14 years 23 days ago
A Small Test Generator for Large Designs
In this paper we report an automatic test pattern generator that can handle designs with one million gates or more on medium size workstations. Run times and success rates, i.e. t...
Sandip Kundu, Leendert M. Huisman, Indira Nair, Vi...
ISCAPDCS
2003
13 years 10 months ago
Utilization of Separate Caches to Eliminate Cache Pollution Caused by Memory Management Functions
Data intensive service functions such as memory allocation/de-allocation, data prefetching, and data relocation can pollute processor cache in conventional systems since the same ...
Mehran Rezaei, Krishna M. Kavi
CODES
2001
IEEE
14 years 11 days ago
Retargetable compilation for low power
Most research to date on energy minimization in DSP processors has focuses on hardware solution. This paper examines the software-based factors affecting performance and energy co...
Wen-Tsong Shiue
PLDI
1995
ACM
14 years 7 days ago
Improving Balanced Scheduling with Compiler Optimizations that Increase Instruction-Level Parallelism
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
Jack L. Lo, Susan J. Eggers
ISCA
1999
IEEE
95views Hardware» more  ISCA 1999»
14 years 1 months ago
Memory Sharing Predictor: The Key to a Speculative Coherent DSM
Recent research advocates using general message predictors to learn and predict the coherence activity in distributed shared memory (DSM). By accurately predicting a message and t...
An-Chow Lai, Babak Falsafi