643 search results - page 84 / 129 » Using Hardware Counters to Automatically Improve Memory Perf... |
MICRO
2005
IEEE
14 years 2 months ago
2005
IEEE
— In this paper we investigate mapping stream programs (i.e., programs written in a streaming style for streaming architectures such as Imagine and Raw) onto a general-purpose CP...
ASPLOS
2008
ACM
13 years 10 months ago
2008
ACM
Nested paging is a hardware solution for alleviating the software memory management overhead imposed by system virtualization. Nested paging complements existing page walk hardwar...
ASAP
2008
IEEE
13 years 10 months ago
2008
IEEE
Automatic generation of custom instruction processors from high-level application descriptions enables fast design space exploration, while offering very favorable performance and...
ISCA
1998
IEEE
14 years 1 months ago
1998
IEEE
Modern cache designs exploit spatial locality by fetching large blocks of data called cache lines on a cache miss. Subsequent references to words within the same cache line result...
ICCAD
2009
IEEE
13 years 6 months ago
2009
IEEE
The emerging Spin Torque Transfer memory (STT-RAM) is a promising candidate for future on-chip caches due to STT-RAM's high density, low leakage, long endurance and high acce...