Sciweavers

850 search results - page 97 / 170
» Using Machine Learning to Guide Architecture Simulation
Sort
View
ISSS
1999
IEEE
131views Hardware» more  ISSS 1999»
14 years 11 days ago
Compressed Code Execution on DSP Architectures
Decreasing the program size has become an important goal in the design of embedded systems target to mass production. This problem has led to a number of efforts aimed at designin...
Paulo Centoducatte, Ricardo Pannain, Guido Araujo
IPPS
1994
IEEE
14 years 6 days ago
Parallel Evaluation of a Parallel Architecture by Means of Calibrated Emulation
A parallel transputer-based emulator has been developed to evaluate the DDM--ahighlyparallel virtual shared memory architecture. The emulator provides performance results of a har...
Henk L. Muller, Paul W. A. Stallard, David H. D. W...
ISCA
2002
IEEE
115views Hardware» more  ISCA 2002»
14 years 1 months ago
ReVive: Cost-Effective Architectural Support for Rollback Recovery in Shared-Memory Multiprocessors
This paper presents ReVive, a novel general-purpose rollback recovery mechanism for shared-memory multiprocessors. ReVive carefully balances the conflicting requirements of avail...
Milos Prvulovic, Josep Torrellas, Zheng Zhang
CIRA
2007
IEEE
147views Robotics» more  CIRA 2007»
14 years 2 months ago
Local Online Support Vector Regression for Learning Control
—Support vector regression (SVR) is a class of machine learning technique that has been successfully applied to low-level learning control in robotics. Because of the large amoun...
Younggeun Choi, Shin-Young Cheong, Nicolas Schweig...
CASES
2008
ACM
13 years 10 months ago
Multiple sleep mode leakage control for cache peripheral circuits in embedded processors
This paper proposes a combination of circuit and architectural techniques to maximize leakage power reduction in embedded processor on-chip caches. It targets cache peripheral cir...
Houman Homayoun, Mohammad A. Makhzan, Alexander V....