610 search results - page 88 / 122 » Using SAT in QBF |
DAC
1998
ACM
14 years 8 months ago
1998
ACM
Abstract-Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model des...
VLSID
2004
IEEE
14 years 8 months ago
2004
IEEE
This paper presents a novel technique for abstracting designs in order to increase the efficiency of formal property checking. Bounded Model Checking (BMC), using Satisfiability (...
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
We propose the redundancy identification of wire replacement faults. The solutions rely on the satisfiability (SAT) formulation of redundancy identification, augmented with the me...
MEMBRANE
2005
Springer
14 years 1 months ago
2005
Springer
In the present paper we propose a way to simulate Boolean gates and circuits in the framework of P systems with active membranes using inhibiting/de-inhibiting rules. This new appr...
LPNMR
2004
Springer
14 years 1 months ago
2004
Springer
A conflict clause represents a backtracking solver’s analysis of why a conflict occurred. This analysis can be used to further prune the search space and to direct the search h...