296 search results - page 21 / 60 » Using SAT-based techniques in power estimation |
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
USENIX
2003
13 years 9 months ago
2003
Despite constant improvements in fabrication technology, hardware components are consuming more power than ever. With the everincreasing demand for higher performance in highly-in...
EUC
2004
Springer
14 years 1 months ago
2004
Springer
We propose power-aware on-line task scheduling algorithms for mixed task sets which consist of both periodic and aperiodic tasks. The proposed algorithms utilize the execution beha...
WCNC
2008
IEEE
14 years 2 months ago
2008
IEEE
—UWB technology can reach centimetre level ranging and positioning accuracy in LOS propagation when time of arrival techniques are used. However, in a real positioning system, th...
VLSID
2007
IEEE
14 years 8 months ago
2007
IEEE
The problem of peak power estimation in CMOS circuits is essential for analyzing the reliability and performance of circuits at extreme conditions. The Power Virus problem involves...