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» Using SAT-based techniques in power estimation
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ISQED
2007
IEEE
140views Hardware» more  ISQED 2007»
14 years 2 months ago
Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays
We propose a methodology and power models for an accurate high-level power estimation of physically partitioned and power-gated SRAM arrays. The models offer accurate estimation o...
Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-...
ISVLSI
2007
IEEE
160views VLSI» more  ISVLSI 2007»
14 years 2 months ago
On the Limitations of Power Macromodeling Techniques
Although RTL power macromodeling is a mature research topic, it is not yet broadly accepted in the industrial environment. One of the main reasons impairing its widespread use as ...
Felipe Klein, Guido Araujo, Rodolfo Azevedo, Rober...
ICCAD
2003
IEEE
175views Hardware» more  ICCAD 2003»
14 years 4 months ago
Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis
Transient Signal Analysis (TSA) is a parametric device testing technique based on the analysis of dynamic (transient) current (iDDT) drawn by the core logic from the power supply ...
Abhishek Singh, Jitin Tharian, Jim Plusquellic
CODES
2010
IEEE
13 years 5 months ago
Accurate online power estimation and automatic battery behavior based power model generation for smartphones
This paper describes PowerBooter, an automated power model construction technique that uses built-in battery voltage sensors and knowledge of battery discharge behavior to monitor...
Lide Zhang, Birjodh Tiwana, Zhiyun Qian, Zhaoguang...
FPL
2010
Springer
131views Hardware» more  FPL 2010»
13 years 5 months ago
Reducing Power Consumption of an Embedded DSP Platform through the Clock-Gating Technique
The paper describes application of the clock-gating techniques, often used in ASIC designs, to the field of FPGAbased systems. The clock-gating techniques are used to reduce the to...
Antonin Hermanek, Michal Kunes, Milan Tichý