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» Using embedded FPGAs for SoC yield improvement
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SBACPAD
2007
IEEE
129views Hardware» more  SBACPAD 2007»
14 years 1 months ago
Predicting Loop Termination to Boost Speculative Thread-Level Parallelism in Embedded Applications
The necessity of devising novel thread-level speculation (TLS) techniques has become extremely important with the growing acceptance of multi-core architectures by the industry. H...
Md. Mafijul Islam
FPGA
2005
ACM
97views FPGA» more  FPGA 2005»
14 years 28 days ago
Techniques for synthesizing binaries to an advanced register/memory structure
Recent works demonstrate several benefits of synthesizing software binaries onto FPGA hardware, including incorporating hardware design into established software tool flows with m...
Greg Stitt, Zhi Guo, Walid A. Najjar, Frank Vahid
CVPR
2012
IEEE
11 years 9 months ago
Image categorization using Fisher kernels of non-iid image models
The bag-of-words (BoW) model treats images as an unordered set of local regions and represents them by visual word histograms. Implicitly, regions are assumed to be identically an...
Ramazan Gokberk Cinbis, Jakob J. Verbeek, Cordelia...
FCCM
2008
IEEE
133views VLSI» more  FCCM 2008»
14 years 1 months ago
Autonomous System on a Chip Adaptation through Partial Runtime Reconfiguration
This paper presents a proto-type autonomous signal processing system on a chip. The system is architected such that high performance digital signal processing occurs in the FPGA...
Matthew French, Erik Anderson, Dong-In Kang
ICCAD
2006
IEEE
127views Hardware» more  ICCAD 2006»
14 years 4 months ago
Platform-based resource binding using a distributed register-file microarchitecture
Behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the underlying platform features. This paper presents a platform-based ...
Jason Cong, Yiping Fan, Wei Jiang