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ASPDAC
2008
ACM
97views Hardware» more  ASPDAC 2008»
13 years 9 months ago
A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures
Horizontally Partitioned Caches (HPCs) are a promising architectural feature to reduce the energy consumption of the memory subsystem. However, the energy reduction obtained using...
Aviral Shrivastava, Ilya Issenin, Nikil Dutt
ICCAD
2002
IEEE
103views Hardware» more  ICCAD 2002»
14 years 4 months ago
Synthesis of customized loop caches for core-based embedded systems
Embedded system programs tend to spend much time in small loops. Introducing a very small loop cache into the instruction memory hierarchy has thus been shown to substantially red...
Susan Cotterell, Frank Vahid
DATE
2010
IEEE
181views Hardware» more  DATE 2010»
14 years 13 days ago
Temperature-aware dynamic resource provisioning in a power-optimized datacenter
- The current energy and environmental cost trends of datacenters are unsustainable. It is critically important to develop datacenter-wide power and thermal management (PTM) soluti...
Ehsan Pakbaznia, Mohammad Ghasemazar, Massoud Pedr...
ISQED
2008
IEEE
154views Hardware» more  ISQED 2008»
14 years 1 months ago
Error Protected Data Bus Inversion Using Standard DRAM Components
Off-chip communication consumes a significant part of main memory system power. Existing solutions imply the use of specialized memories or assume error free environments. This i...
Maurizio Skerlj, Paolo Ienne
SCOPES
2007
Springer
14 years 1 months ago
Optimization of dynamic data structures in multimedia embedded systems using evolutionary computation
Embedded consumer devices are increasing their capabilities and can now implement new multimedia applications reserved only for powerful desktops a few years ago. These applicatio...
David Atienza, Christos Baloukas, Lazaros Papadopo...